Conventional virtual-phase CCD imager arrays comprise a plurality of virtual-phase cells, each having a virtual barrier, a virtual well, a clocked barrier and a clocked well all formed at a face of a semiconductor substrate. Conventionally, these arrays are operated in an integration step and a charge transfer step. During the integration step, charge is integrated in the virtual well of each of the cells. During the charge transfer step, a voltage bias on the device gates is increased from a low voltage to a high voltage in order to transfer the charge from the virtual well to an adjacent clocked well. This voltage bias is then removed in order to transfer the charge to a next adjacent virtual well. The charges are thus moved from well to well until the end of the array is reached, wherein the charges are transferred into cells of a serial register and then read out, one row of cells at a time.
Certain conventional CCD imager cells include an antiblooming drain, wherein an excess of charge built up during an integration step may be transferred through a drain barrier to a drain, thus preventing the transfer of the excess charge over to other virtual wells or "blooming". However, in conventional structures blooming level cannot be easily independently adjusted, and additional structures such as implanted barriers or gates must be added.
It has become desirable to construct a CCD imager array for television interlace operation. In an interlace mode, two fields of rows or lines of the CCD imager array cells are successively read. First, a field of odd lines is read, one after the other. Then, a field of even lines in between the odd lines is read, one after the other. A need thus exists for a CCD imager array adaptable to TV interlace operation that further includes a simple, independently adjustable antiblooming feature that can be incorporated without adding any additional mask steps in the fabrication process.
There are also a number of applications where it is necessary to generate a mirror image from a camera. In the past, this was accomplished by one of several methods, including reversing the electron beam scan in a TV pickup tube or reversing the electron beam scan in the display medium such as a CRT tube.
With the advent of solid stage image sensors, it is usually not possible to reverse the scan in the image sensor, since the scanning direction is preselected. This is particularly true in single- or two- phase structures where the directionality is built in bY ion implantation. This presents a disadvantage in applications with mirror image sensing, since a new device is necessary to be designed for this case. A need has therefore arisen to provide an on-chip output register that can selectively read out a true image or a mirror image.